Offload Multiple Signal Classification (MUSIC) to AMD Versal™ AI Engines

Presenters:

• Bachir Berkane, System and Algorithm Architect at Fidus Systems
• Peifang Zhou, Senior Embedded Software Designer at Fidus Systems
• Mark Rollins, Ph.D., Sr. Manager Technical Marketing at AMD
  

Duration: 60 minutes

Missed the live webinar? No worries! You can now access the on-demand version of our insightful webinar.

In partnership with AMD, join us for an in-depth presentation on how high-performance DSP algorithms can be accelerated using AMD Versal AI Engine technology. We showcase the implementation of a MUSIC (Multiple Signal Classification) algorithm—widely adopted in radar, sonar, and wireless systems—to demonstrate the advanced compute capabilities of Versal Adaptive SoCs.

MUSIC algorithms are deployed across applications requiring:

•    Direction of Arrival (DOA) estimation
•    Frequency & Spectral Estimation
•    Modal Analysis
•    Blind Source Separation

Due to their significant computational demands, MUSIC algorithms are ideal candidates for acceleration using Versal AI Engines. This project, developed in collaboration between AMD and Fidus Systems, demonstrates how real-time performance was achieved using efficient C/C++ kernel development and pipelined AI Engine tile architectures.

Why watch the webinar?

• End-to-End Implementation of the MUSIC Algorithm:
  Gain a complete understanding of how Multiple Signal Classification (MUSIC) is structured and deployed—from signal modeling and QR decomposition to SVD-based subspace separation and spatial spectrum analysis for Direction of Arrival (DOA) estimation.
• Real-Time Performance Using AMD Versal AI Engines:
  See how Fidus mapped MUSIC onto AMD’s Versal AI Engine array, achieving a 1 microsecond throughput using 150 tiles with fully pipelined, vectorized kernel implementations in C/C++.
• AI Engine Architecture Deep Dive:
  Explore the 2D array of VLIW processors and memory tiles that power Versal’s AI Engine, including details on SIMD vector units, instruction-level parallelism (7-way VLIW), and deterministic interconnect strategies for high-performance DSP workloads.
• Loop Unrolling and Tile Mapping Strategy:
  Understand how key algorithm components—QRD, SVD, spectrum computation, and DOA search—were transformed into deep pipeline stages using loop unrolling, efficient data movement, and local memory sharing between tiles.
• Hardware-in-the-Loop (HIL) Demonstration:
  Watch a real-time demo that integrates MATLAB snapshot generation with MUSIC execution on the AMD VCK190 evaluation board. See how results—including DOA plots and spectrum profiles—are visualized and validated over TCP/IP.
• C/C++ Design Best Practices for AI Engine:
  Learn how the Fidus team used compiler directives, data-level parallelism, and static memory optimization to maximize performance, plus lessons learned shared via published design blogs.
• Scalability and Future Use Cases:
  Discover how this approach can scale to larger antenna arrays, more sources, or finer resolution bins—and how these techniques apply to frequency estimation, biomedical signal processing, and structural vibration analysis.
• Collaboration Insights from AMD and Fidus:
  See how the joint effort leveraged AMD’s latest toolchains and the expertise of Fidus—AMD’s Adaptive Computing Partner of the Year—to validate design flows and deliver a complete reference implementation.
  

This webinar is ideal for:

• Radar and Wireless  System Architects
• FPGA Design and DSP Engineers
• Embedded Software Developers
• System Architects
• VPs of Engineering and Product Development
• CTOs and R&D Managers