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Strategies for optimizing FPGA designs with AMD Versal Adaptive SoCs


  • Date: Tuesday, June 4th 2024  
  • Time: 11:30 am EST
  • Presenter: Normand Leclerc, Senior FPGA Designer
Can't make the time? Register anyway and receive the on-demand version!

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Under the guidance of Normand Leclerc, a seasoned Fidus expert in FPGA design, this webinar will clarify the complexities of integrating and configuring the AMD Versal AI core series. Attendees will learn through a detailed demonstration of setting up a new Vivado project and will gain practical skills in system synthesis, placement, and the strategic use of the Network on Chip (NOC) for efficient data movement and design optimization. 

This webinar is designed for FPGA designers, engineers, technical leads, and anyone interested in enhancing their FPGA design skills specifically on the AMD Versal product.

Why attend?

  • Deep dive into AMD Versal AI: Explore the architecture and capabilities of the AMD Versal AI core series VC1902 adaptive SoC and its application in FPGA designs.
  • Hands-on demonstration: Practical walkthrough of a recent AMD Vivado project setup, showcasing integration and configuration techniques.
  • Expert insights: Led by Normand Leclerc, gain firsthand knowledge of effective FPGA design strategies and the advantages of using the NOC for design partitioning and data movement.

Key learning points:

  • Understanding AMD Versal AI core series: Discover the features and potential of the AMD Versal AI core series, crucial for advancing in FPGA designs.
  • Integrating key system components: Learn how to connect essential components like CIPS, DDR, and AI engines using the NOC, enhancing system performance and efficiency.
  • Optimizing data transfer: Develop skills to optimize data movement across the FPGA chip, employing the NOC for efficient design partitioning, which is key to managing complex designs.
  • Visualizing and configuring NOC structures: Gain insights into the NOC's configuration and learn techniques to visualize its structure, enabling better understanding and use in FPGA projects.

Register for the webinar