Versal designs reward the decisions you make before schematic capture. This guide collects what Fidus engineers have learned designing boards around the AMD Versal™ Adaptive SoC. It is written for hardware engineers and engineering managers who know AMD FPGAs and adaptive SoCs and are planning a Versal design.
What's inside
- Device selection: how the Versal series compare, and how to partition work across the processors, programmable logic and AI Engines.
- I/O and connectivity: MIO and EMIO assignment, Bank 503 and PMC pins, GTY, GTYP and GTM transceivers, PCIe, and XPIO, X5IO and HDIO.
- Power and thermals: rail planning, sequencing and thermal design.
- Memory and data movement: the NoC, PS and PL DDR, HBM and clocking.
- Bring-up and debug: resets, boot modes, debug headers, test points, HSDP and the AMD XTP546 schematic checklist.
- Four project examples: defense, radar, imaging and high-performance computing platforms Fidus has delivered.
Written by Navin Gautam, Senior Hardware Designer, Fidus Systems.
AMD, the AMD Arrow logo, Versal, and combinations thereof are trademarks of Advanced Micro Devices, Inc. Other product names used in this publication are for identification purposes only and may be trademarks of their respective owners.
