---
title: "Watch On Demand: What the PCB Decides at 112G and Beyond | Fidus"
description: "Watch the recording: Dr. Syed Bokhari shows how stackup, vias, BGA breakout and connector footprints decide 112G and 224G PAM4 channel margin."
---

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On-Demand Webinar | Fidus Tech Talk

# What the PCB Decides at 112G and Beyond

Recorded November 5, 2026 Watch anytime 38 min · Talk + Q&A

[Watch the recording](https://info.fidus.com/webinar-what-the-pcb-decides-at-112g-on-demand#FORM)

Starts soon

### **What you'll learn**

01

Stackup and materials

How stackup and material choices set your loss budget before routing starts.

02

Vias and breakout

What via stubs, back-drilling and breakout cost in return loss and crosstalk margin, with numbers from real boards.

03

Discontinuities

Where BGA pads, connector, and AC coupling capacitor footprints create discontinuities, and how to reduce them.

04

The road to 224G and beyond

Why 112G reference channels run short of bandwidth for 224G PAM4.

### **Key details**

- **Format:** On-demand recording, watch anytime
- **Length:** 38 minutes (20-minute technical talk followed by Q&A)
- **Recorded:** November 5, 2026
- **Speaker:** Dr. Syed A. Bokhari, Signal Integrity and EMC Architect, Fidus

**Instant access.** Register and the recording opens right away. We will also email you the link.

### **About this webinar**

At 112G PAM4, and beyond, most of your channel margin is won or lost in the printed circuit board itself. In this Fidus Tech Talk, Signal Integrity Architect Dr. Syed Bokhari walks through a 112G channel, from ASIC to AC coupling capacitor to connector, and shows what each layout decision costs.

Drawing on Fidus printed circuit board and package work rather than textbook examples, Syed covers stackup and material choices, via design and back-drilling, AC capacitor and connector footprints, and reference-plane cutouts. He closes with what changes as the industry moves to 224G, followed by Q&A on microvias, where channel margin goes and how accurate pre-layout loss estimates are.

### Watch the recording

Free · 38 minutes · Instant access

Presenter

![Syed](https://info.fidus.com/hubfs/Syed.png)

### Dr. Syed A. Bokhari

Signal Integrity and EMC Architect, Fidus

Syed has spent decades on PCB design for signal and power integrity, with prior roles at Cadence Design Systems, the University of Ottawa and EPFL in Lausanne, Switzerland.

Chair of the IEEE Ottawa EMC ChapterTechnical Papers Co-Chair of the 2016 IEEE EMC SymposiumEDICON 2017 Outstanding Paper Award in SIDesignCon 2019 best paper finalistTwo patents

Who should watch

## Ideal for engineers and technical leads working in

Signal integrity and high-speed digital designPCB layout and hardware designHardware design with high-speed SerDes and transceiversFPGA and ASIC board bring-upTest and validation engineeringHardware leads planning 112G and 224G platformsData center and networkingAI and HPC acceleratorsTelecom and opticalAerospace and defenseSemiconductorTest and measurement systems

## Watch the full recording

Recorded November 5, 2026 · 38 minutes · Watch on demand

[Watch now](https://info.fidus.com/webinar-what-the-pcb-decides-at-112g-on-demand#FORM)

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